FPGAs, namely Field-programmable gate arrays, emerge as a kind of semi-custom circuits in application specific integrated circuits (ASICs), and are widely applied in various fields such as communication, data processing, network, instruments, industrial control, military and aviation due to their favorable performance and programmable ability as well as low power consumption and cost. However, FPGAs are typically not able to realize complex arithmetic logic in case of controlling costs.
In data processing, X86 architecture platforms have an advantage of strong extendibility, i.e., software running on X86 architecture platforms can support relatively complex arithmetic logics, but the arithmetic capability of X86 architecture platforms typically is not high, which limits their development to a high-end market.
In view of respective features of the above two heterogeneous platforms, an architecture system combining these two heterogeneous platforms, i.e., FPGA+X86 architecture system, has been proposed in prior art.
FIG. 1 shows a view illustrating data interaction between two heterogeneous platforms in a FPGA+X86 architecture system in prior art.
As shown in FIG. 1, in this architecture system, logical processing of X86 platform may proceed only after obtaining shared information, therefore data between the two heterogeneous platforms needs to be synchronized. The shared information is used by FPGA under most forwarding cases, and the fewer cross-platform information inquiries occur, the less influence on the overall performance. For this reason, data sets are usually stored on FPGA. In this case, FPGA does not know when X86 platform needs data, and thus most data acquisitions are initiated by X86 platform.
The synchronized data interaction process between existing X86 platform and FPGA is as follows: the X86 platform initiates an operation instruction via interrupt, FPGA responds to this operation instruction and executes it, and finally FPGA returns result of execution to X86 platform. Thereafter, X86 platform may proceed with processing of subsequent complex logics.
However, since the above process takes a long time, the performance of overall system is greatly consumed. Therefore, in a FPGA+X86 architecture system, it is a key technology and also a technology bottle neck for this system how to deal with synchronization of associated data between the two heterogeneous platforms with high efficiency to ensure consistency of shared data set in the two systems.